Width-Adaptive Data Word Architectures

We discuss number representations for width-adaptive data word architectures. The number representations are self-delimiting, permitting asynchronous implementations with dynamic width adaptivity and reduced energy-complexity. We describe how these architectures can be realized with asynchronous VLSI techniques, and show that they exhibit better energy and throughput characteristics than traditional asynchronous implementations. We study some of the tradeoffs in the design of this class of architectures.